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ltm4612 1 4612fb typical a pplica t ion fea t ures a pplica t ions descrip t ion en55022b compliant 36v in , 15v out , 5a, dc/dc module regulator the ltm ? 4612 is a en55022 class b certified high voltage input and output, 5a switching mode dc/dc power supply. included in the package are the switching controller, power fets, inductor and all support components. operating over an input voltage range of 5v to 36v, the ltm4612 supports an output voltage range of 3.3v to 15v, set by a single resistor. only bulk input and output capacitors are needed to finish the design. high switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. the onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (emi)see figures 4 and 8. furthermore, the dc/dc module ? regulator can be syn- chronized with an external clock to reduce undesirable frequency harmonics and allow polyphase ? operation for high load currents. the ltm4612 is offered in a space saving and thermally enhanced 15mm 15mm 2.8mm lga package, which enables utilization of unused space on the bottom of pc boards for high density point-of-load regulation. the ltm4612 is pb-free and rohs compliant. l , lt, ltc, ltm, linear technology, the linear logo, polyphase and module are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 5v/5a ultralow noise module with 7v to 36v input n complete low emi switch mode power supply n en55022 class b compliant n wide input voltage range: 5v to 36v n 3.3v to 15v output voltage range n 5a dc, 7a peak output current n low input and output referred noise n output voltage tracking and margining n power good tracks with margining n pll frequency synchronization n 1.5% set point accuracy n current foldback protection (disabled at start-up) n parallel/current sharing n ultrafast transient response n current mode control n programmable soft-start n output overvoltage protection n C55c to 125c operating temperature range (l tm4612mpv) n small surface mount footprint, low profile (15mm 15mm 2.8mm) lga package n telecom and networking equipment n industrial and avionic equipment n rf systems radiated emission scan at 24v in , 5v out /5a frequency (mhz) 30 dbv/m 30 70 128.1 226.2 324.3 10 60 20 0 ?10 50 40 422.4 520.5 618.6 716.7 814.8 912.9 1010 en55022 class b limit 4612 ta01b pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb v in 0.01f 10f 100pf c out v out 5v 5a c in v in 7v to 36v pllin clock sync ltm4612 sgnd v d pgnd margin control 100k 2m 13.7k 392k 5% margin 4612 ta01
ltm4612 2 4612fb p in c on f igura t ion a bsolu t e maxi m u m r a t ings intv cc, drv cc ............................................. C0 .3v to 6v v out ........................................................... C0 .3v to 16v pllin, fcb, track/ss, mpgm, marg0, marg1, pgood .................... C 0.3v to intv cc + 0.3v run ............................................................. C 0.3v to 5v v fb , comp ................................................ C0 .3v to 2.7v v in , v d ....................................................... C0 .3v to 36v internal operating temperature range (note 2) e and i g rades ................................... C 40c to 125c mp g rade ........................................... C 55c to 125c junction temperature ........................................... 1 25c storage temperature range .................. C 55c to 125c (note 1) marg1 drv cc v fb pgood sgnd nc nc nc fcb v in bank 1 v d pgnd bank 2 v out bank 3 f set marg0 run comp mpgm pllin intv cc track/ss lga package 133-lead (15mm 15mm 2.8mm) top view sgnd 12 21 43 5 6 98 10 11 7 a b c d e f g h j k l m t jmax = 125c, ja = 15c/w, jc = 6c/w ja derived from 95mm 76mm pcb with 4 layers weight = 1.7g or d er in f or m a t ion lead free finish tray part marking* package description temperature range ltm4612ev#pbf ltm4612ev#pbf ltm4612v 133-lead (15mm 15mm 2.8mm) lga C40c to 125c ltm4612iv#pbf ltm4612iv#pbf ltm4612v 133-lead (15mm 15mm 2.8mm) lga C40c to 125c ltm4612mpv#pbf ltm4612mpv#pbf ltm4612mpv 133-lead (15mm 15mm 2.8mm) lga C55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in(dc) input dc voltage l 5 36 v v out(dc) output voltage c in = 10f 3, c out = 300f; fcb = 0 v in = 24v, v out = 12v, i out = 0a v in = 36v, v out =12v, i out = 0a l l 11.83 11.83 12.07 12.07 12.31 12.31 v v input specifications v in(uvlo) undervoltage lockout threshold i out = 0a 3.2 4.8 v i inrush(vin) input inrush current at start-up i out = 0a; c in = 10f 2, c out = 200f; v out = 12v v in = 24v v in = 36v 0.6 0.7 a a the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, unless otherwise noted (note 2). per typical application (front page) configuration.
ltm4612 3 4612fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, unless otherwise noted (note 2). per typical application (front page) configuration. symbol parameter conditions min typ max units i q(vin) input supply bias current v in = 36v, v out = 12v, switching continuous v in = 24v, v out = 12v, switching continuous shutdown, run = 0, v in = 36v 57 48 50 ma ma a i s(vin) input supply current v in = 36v, v out = 12v, i out = 5a v in = 24v, v out = 12v, i out = 5a 1.85 2.72 a a v intvcc internal v cc voltage v in = 36v, run > 2v, i out = 0a 4.7 5 5.3 v output specifications i out(dc) output continuous current range v in = 24v, v out = 12v (note 4) 0 5 a dv out(line) v out line regulation accuracy v out = 12v, fcb = 0v, v in = 22v to 36v, i out = 0a l 0.05 0.3 % dv out(load) v out load regulation accuracy v out = 12v, fcb = 0v, i out = 0a to 5a (note 4) v in = 36v v in = 24v l l 0.3 0.3 0.6 0.6 % % v in(ac) input ripple voltage i out = 0a, c in = 2 10f x5r ceramic and 1 100f electrolytic, 1 10f x5r ceramic on v d pins v in = 24v, v out = 5v v in = 24v, v out = 12v 7.2 3.4 mv p-p mv p-p v out(ac) output ripple voltage i out = 0a, c out = 2 22f, 2 47f x5r ceramic v in = 24v, v out = 5v v in = 24v, v out = 12v 17.5 12.5 mv p-p mv p-p f s output ripple voltage frequency i out = 1a, v in = 24v, v out = 12v 940 khz dv out(start) turn-on overshoot, track/ss = 10nf c out = 200f, v out = 12v, i out = 0a v in = 36v v in = 24v 20 20 mv mv t start turn-on time, track/ss = open c out = 300f, v out = 12v, i out = 1a resistive load v in = 36v v in = 24v 0.5 0.5 ms ms dv out(ls) peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 2 22f ceramic, 150f bulk v in = 24v, v out = 12v 153 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, v in = 24v 37 s i out(pk) output current limit c out = 200f v in = 36v, v out = 12v v in = 24v, v out = 12v 9 9 a a control section v fb voltage at v fb pin i out = 0a, v out = 12v l 0.591 0.6 0.609 v v run run pin on/off threshold 1 1.5 1.9 v i ss / track soft-start charging current v ss / track = 0v C1 C1.5 C2 a v fcb forced continuous threshold 0.57 0.6 0.63 v i fcb forced continuous pin current v fcb = 0v C1 C2 a t on(min) minimum on-time (note 3) 50 100 ns t off(min) minimum off-time (note 3) 250 400 ns r pllin pllin input resistor 50 kw
ltm4612 4 4612fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4612e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4612i is guaranteed to meet specifications over the symbol parameter conditions min typ max units i drvcc current into drv cc pin v out = 12v, i out = 1a 22 30 ma r fbhi resistor between v out and v fb pins 99.5 100 100.5 k w v mpgm margin reference voltage 1.18 v v marg0 , v marg1 marg0, marg1 voltage thresholds 1.4 v pgood dv fbh pgood upper threshold v fb rising 7 10 13 % dv fbl pgood lower threshold v fb falling C7 C10 C13 % dv fb(hys) pgood hysteresis v fb returning 1.5 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, unless otherwise noted (note 2). per typical application (front page) configuration. C40c to 125c internal operating temperature range. the ltm4612mp is guaranteed and tested over the full C55c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: 100% tested at die level only. note 4: see the output current derating curves for different v in , v out and t a .
ltm4612 5 4612fb typical p er f or m ance c harac t eris t ics efficiency vs load current with 3.3v out (fcb = 0) efficiency vs load current with 5v out (fcb = 0) efficiency vs load current with 12v out (fcb = 0) efficiency vs load current with 15v out (fcb = 0, refer to figure 20) transient response from 12v in to 3.3v out transient response from 12v in to 5v out transient response from 24v in to 12v out start-up with 24v in to 12v out at i out = 0a start-up with 24v in to 12v out at i out = 5a (refer to figure 18) load current (a) 0 efficiency (%) 70 95 100 1 2 3 60 85 65 90 55 50 80 75 4 5 4612 g01 5v in 3.3v out 12v in 3.3v out 24v in 3.3v out 36v in 3.3v out load current (a) 0 efficiency (%) 70 95 1 2 3 60 85 65 90 55 50 80 75 4 5 4612 g02 12v in 5v out 24v in 5v out 36v in 5v out load current (a) 0 efficiency (%) 70 95 100 1 2 3 60 85 65 90 55 50 80 75 4 5 4612 g03 20v in 12v out 24v in 12v out 28v in 12v out 36v in 12v out load current (a) 0 efficiency (%) 70 100 95 1 2 3 60 85 65 90 80 75 4 5 4612 g04 28v in 15v out 32v in 15v out 36v in 15v out 50s/div 2a/div 100mv/div 4612 g05 load step: 0a to 3a c out = 2 22f ceramic capacitors and 2 47f ceramic capacitors 50s/div 2a/div 100mv/div 4612 g06 load step: 0a to 3a c out = 2 22f ceramic capacitors and 2 47f ceramic capacitors 50s/div 2a/div 200mv/ div 4612 g07 load step: 0a to 3a c out = 2 22f ceramic capacitors and 2 47f ceramic capacitors 500s/div i in 0.2a/div v out 5v/div 4612 g08 soft-start capacitor: 3.9nf c in = 3 10f ceramic capacitors and 1 47f oscon capacitor 500s/div i in 1a/div v out 5v/div 4612 g09 soft-start capacitor: 3.9nf c in = 3 10f ceramic capacitors and 1 47f oscon capacitor
ltm4612 6 4612fb typical p er f or m ance c harac t eris t ics start-up with 24v in to 12v out at i out = 5a, t a = C55c short-circuit with 24v in to 12v out at i out = 0a short-circuit with 24v in to 12v out at i out = 5a v in to v out step-down ratio input ripple output ripple 500s/div i in 1a/div v out 5v/div 4612 g10 soft-start capacitor: 3.9nf c in = 3 10f ceramic capacitors and 1 47f oscon capacitor 50s/div i in 0.2a/div v out 5v/div 4612 g11 c out = 2 22f ceramic capacitors and 2 47f ceramic capacitors 20s/div i in 2a/div v out 5v/div 4612 g12 c out = 2 22f ceramic capacitors and 2 47f ceramic capacitors 3.3 24 30 18 12 6 10 4 8 12 14 15 6 0 36 4612 g13 see frequency adjustment section for operations outside this region operating region with default frequency v out (v) v in (v) 1s/div 50mv/div 4612 g14 v in = 24v v out = 12v at 5a resistive load c in = 3 10f 50v ceramic 1 100f bulk 1s/div 10mv/div 4612 g15 v in = 24v v out = 12v at 5a resistive load c out = 2 22f 16v ceramic and 2 47f 16v ceramic
ltm4612 7 4612fb p in func t ions v in (bank 1): power input pins. apply input voltage be- tween these pins and pgnd pins. recommend placing input decoupling capacitance directly between v in pins and pgnd pins. pgnd (bank 2): power ground pins for both input and output returns. v out (bank 3): power output pins. apply output load between these pins and pgnd pins. recommend placing out- put decoupling capacitance directly between these pins and gnd pins (see the ltm4612 pin configuration below). v d (pins b7, c7): top fet drain pins. add more capa- citors between v d and ground to handle the input rms current and reduce the input ripple further. drv cc (pins c10, e11, e12): these pins normally connect to intv cc for powering the internal mosfet drivers. they can be biased up to 6v from an external supply with about 50ma capability. this improves efficiency at higher input voltages by reducing power dissipation in the module. intv cc (pin a7): this pin is for additional decoupling of the 5v internal regulator. pllin (pin a8): external clock synchronization input to the phase detector. this pin is internally terminated to sgnd with a 50k resistor. apply a clock above 2v and below intv cc . see the applications information section. fcb (pin m12): forced continuous input. connect this pin t o sgnd to force continuous synchronization operation at low load, to intv cc to enable discontinuous mode opera- tion at low load or to a resistive divider from a secondary output when using a secondary winding. track/ss (pin a9): output voltage tracking and soft-start pin. when the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. a soft-start capacitor can be used for soft-start turn-on as a standalone regulator. slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. see the applications information section. mpgm (pins a12, b11): programmable margining in- put. a resistor from these pins to ground sets a current that is equal to 1.18v/r. this current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6v reference voltage. may be left open if margining is not desired. see the applications information section. to parallel ltm4612s, each requires an individual mpgm resistor. do not tie mpgm pins together. f set (pin b12): frequency set internally to ~850khz to 900khz at 12v output. an external resistor can be placed from this pin to ground to increase frequency. see the applications information section for frequency adjustment. ltm4612 pin configuration (see package description for pin assignments) marg1 drv cc v fb pgood sgnd nc nc nc fcb v in bank 1 v d pgnd bank 2 v out bank 3 f set marg0 run comp mpgm pllin intv cc track/ss lga package 133-lead (15mm 15mm 2.8mm) top view sgnd 12 21 43 5 6 98 10 11 7 a b c d e f g h j k l m
ltm4612 8 4612fb v fb (pin f12): the negative input of the error ampli- fier. internally, this pin is connected to v out with a 100k 0.5% precision resistor. different output voltages can be programmed with an additional resistor between the v fb and sgnd pins. see the applications information section. marg0 (pin c12): lsb logic input for the margining function. together with the marg1 pin, the marg0 pin will determine if a margin high, margin low, or no margin state is applied. the pin has an internal pull-down resistor of 50k. see the applications information section. marg1 (pins c11, d12): msb logic input for the margin- ing function. together with the marg0 pin, the marg1 pin will determine if a margin high, margin low, or no margin state is applied. the pins have an internal pull-down resistor of 50k. see the applications information section. sgnd (pins d9, h12): signal ground pins. these pins connect to pgnd at output capacitor point. comp (pins a11, d11): current control threshold and error amplifier compensation point. the current com- parator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.7v corresponding to zero sense voltage (zero current). pgood (pin g12): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after a 25s power bad mask timer expires. run (pins a10, b9): run control pins. a voltage above 1.9v will turn on the module, and below 1v will turn off the module. a programmable uvlo function can be ac- complished with a resistor from v in to this pin that is has a 5.1v zener to ground. maximum pin voltage is 5v. nc (pins j12, k12, l12): no connect pins. leave floating. p in func t ions
ltm4612 9 4612fb b lock diagra m d ecoupling require m en t s symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 20v to 36v, v out = 12v) i out = 4a 20 f c out external output capacitor requirement (v in = 20v to 36v, v out = 12v) i out = 4a 100 150 f specifications are at t a = 25c. use figure 1 configuration. + internal comp sgnd comp pgood run > 1.9v = on < 1v = off max = 5v marg1 marg0 mpgm fcb pllin c ss intv cc drv cc track/ss v fb f set 50k 93.1k r fb 5.23k 50k 100k v out 5.1v zener power control m1 v in 20v to 36v v d v out 12v at 4a m2 50k 10f 1f c in + c out pgnd 4612 f01 c d 10k 4.7f input filter 2.7h noise cancel- lation figure 1. simplified block diagram
ltm4612 10 4612fb o pera t ion power module description the ltm4612 is a standalone nonisolated switching mode dc/dc power supply. it can deliver 5a of dc output current with some external input and output capacitors. this module provides precisely regulated output voltage programmable via one external resistor from 3.3v dc to 15v dc over a 5v to 36v wide input voltage. the typical application schematic is shown in figure 18. the ltm4612 has an integrated constant on-time current mode regulator, ultralow r ds(on) fets with fast switching speed and integrated schottky diodes. the typical switching frequency is 850khz at full load at 12v output. with current mode control and internal feedback loop compensation, the ltm4612 module has sufficient stability margins and good transient performance under a wide range of operat - ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limiting. moreover, foldback current limiting is provided in an overcurrent condition while v fb drops. internal over - voltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. furthermore, in an overvoltage condition, internal top fet m1 is turned off and bottom fet m2 is turned on and held on until the overvoltage condition clears. input filter and noise cancellation circuitry reduce the noise coupling to i/o sides, and ensure the electromagnetic interference (emi) meets the limits of en55022 class b. pulling the run pin below 1v forces the controller into its shutdown state, turning off both m1 and m2. at light load currents, discontinuous mode (dcm) operation can be enabled to achieve higher efficiency compared to con- tinuous mode (ccm) by setting fcb pin higher than 0.6v. when the drv cc pin is connected to intv cc , an integrated 5v linear regulator powers the internal gate drivers. if a 5v external bias supply is applied on drv cc pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. this is especially true at higher input voltages. the mpgm, marg0, and marg1 pins are used to sup- port output voltage margining, where the percentage of margin is programmed by the mpgm pin, and the marg0 and marg1 select margining. the pllin pin provides frequency synchronization of the device to an external clock. the track/ss pin is used for power supply track- ing and soft-start programming. the typical ltm4612 application circuit is shown in figure 18. external component selection is primarily determined by the maximum load current and output voltage. refer to table 2 for specific external capacitor requirements for a particular application. a pplica t ions i n f or m a t ion v in to v out stepdown ratios there are restrictions in the maximum v in and v out step down ratio that can be achieved for a given input voltage. these constraints are shown in the typical performance characteristic curve labeled v in to v out step-down ratio. note that additional thermal derating may be ap - plied. see the thermal considerations and output current derating section in this data sheet.
ltm4612 11 4612fb a pplica t ions i n f or m a t ion output voltage programming and margining the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 100k internal feedback resistor connects the v out and v fb pins together. adding a resistor, r fb , from the v fb pin to the sgnd pin programs the output voltage. v out = 0.6v ? 100k + r fb r fb or equivalently, r fb = 100k v out 0.6v ? 1 table 1. r fb standard 1% resistor values vs v out v out (v) 3.3 5 6 8 10 12 14 15 r fb (kw) 22.1 13.7 11 8.06 6.34 5.23 4.42 4.12 the mpgm pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6v reference offset for margining. a 1.18v reference divided by the table 2. output voltage response vs component matrix (refer to figure 20) typical measured values vendors part number vendors part number murata grm32er61c476kei5l (47f, 16v) murata grm32er71h106k (10f, 50v) murata grm32er61c226ke20l (22f, 16v) tdk c3225x5ric226m (22f, 16v) v out (v) c in (ceramic) c in (bulk) c out1 (ceramic) c out2 (bulk) v in (v) droop (mv) peak-to- peak (mv) recovery time (s) load step (a/s) r fb (k) 5 2 10f 50v 100f 50v 2 22f 16v 150f 25v 12 86 156 26 3 13.7 5 2 10f 50v 100f 50v 4 47f 16v none 12 86 178 14.8 3 13.7 5 2 10f 50v 100f 50v 2 22f 16v 150f 25v 24 83 166 27 3 13.7 5 2 10f 50v 100f 50v 4 47f 16v none 24 86 169 14.8 3 13.7 5 2 10f 50v 100f 50v 2 22f 16v 150f 25v 36 86 178 25 3 13.7 5 2 10f 50v 100f 50v 4 47f 16v none 36 86 172 15.2 3 13.7 10 2 10f 50v 100f 50v 2 22f 16v 150f 25v 24 111 209 30 3 6.34 10 2 10f 50v 100f 50v 4 47f 16v none 24 171 325 35 3 6.34 10 2 10f 50v 100f 50v 2 22f 16v 150f 25v 36 108 197 35 3 6.34 10 2 10f 50v 100f 50v 4 47f 16v none 36 153 288 39 3 6.34 12 2 10f 50v 100f 50v 2 22f 16v 150f 25v 24 153 281 37 3 5.23 12 2 10f 50v 100f 50v 4 47f 16v none 36 184 375 34.4 3 5.23 15 2 10f 50v 100f 50v 2 22f 16v 150f 25v 28 178 338 70 3 4.12 15 2 10f 50v 100f 50v 4 47f 16v none 36 134 250 70 3 4.12 r pgm resistor on the mpgm pin programs the current. calculate v out(margin) : v out(margin) = %v out 100 ? v out where %v out is the percentage of v out to be margined, and v out(margin) is the margin quantity in volts: r pgm = v out 0.6v ? 1.18v v out(margin) ? 10k where r pgm is the resistor value to place on the mpgm pin to ground. the output margining will be margining of the value. this is controlled by the marg0 and marg1 pins. see the truth table below: marg1 marg0 mode low low no margin low high margin up high low margin down high high no margin
ltm4612 12 4612fb a pplica t ions i n f or m a t ion operating frequency the operating frequency of the ltm4612 is optimized to achieve the compact package size and the minimum output ripple voltage while still providing high efficiency. as shown in figure 2, the frequency is linearly increased with larger output voltages to keep the low output cur - rent ripple. figure 3 shows the inductor current ripple di with different output voltages. in most applications, no additional frequency adjusting is required. if lower output ripple is required, the operating frequency f can be increased by adding a resistor r fset between f set pin and sgnd, as shown in figure 19. f = v out 1.5 ? 10 ? 10 r fset || 93.1k ( ) figure 2. operating frequency vs output voltage figure 3. inductor current ripple vs output voltage v out (v) 2 600 800 1200 8 12 4612 f02 400 4 6 10 14 16 200 1000 frequency (khz) 2 2.5 3.0 2.0 1.5 6 10 4 8 12 14 16 1.0 0.5 3.5 4612 f03 v in = 36v v in = 28v v in = 20v v out (v) inductor current ripple ?i (a) for output voltages more than 12v, the frequency can be higher than 1mhz, thus reducing the efficiency significantly. additionally, the 500ns minimum off time (400ns + 100ns for margin) normally limits the operation when the input voltage is close to the output voltage. therefore, it is rec- ommended to lower the frequency in these conditions by connecting a resistor (r fset ) from the f set pin to v in , as shown in figure 20. f = v out 5 ? 10 ? 11 3 ? r fset ? 93.1k r fset ? 2 ? 93.1k ? ? ? ? ? ? the load current can affect the frequency due to its constant on-time control. if constant frequency is a necessity, the pllin pin can be used to synchronize the frequency of the ltm4612 to an external clock, as shown in figures 21 to 23.
ltm4612 13 4612fb figure 4. radiated emission scan with 24v in to 5v out at 5a (2 10f ceramic capacitors on v in pads and 1 10f ceramic capacitor on v d pads) a pplica t ions i n f or m a t ion input capacitors ltm4612 is designed to achieve the low input radiated emi noise due to the fast switching of turn-on and turn-off. in the ltm4612, a high-frequency inductor is integrated into the input line for noise attenuation. v d and v in pins are available for external input capacitors to form a high frequency filter. as shown in figure 18, the ceramic capacitor c1 on the v d pins is used to handle most of the rms current into the converter, so careful attention is needed for capacitor c1 selection. for a buck converter, the switching duty cycle can be estimated as: d = v out v in without considering the inductor current ripple, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) h ? d ? 1C d ( ) in this equation, h is the estimated efficiency of the power module. note the capacitor ripple current ratings are often based on temperature and hours of life. this makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. always contact the capacitor manufacturer for derating requirements. in a typical 5a output application, one very low esr, x5r or x7r, 10f ceramic capacitor is recommended for c1. this decoupling capacitor should be placed directly adja- cent to the module v d pins in the pcb layout to minimize the trace inductance and high frequency ac noise. each 10f ceramic is typically good for 2a to 3a of rms ripple current. refer to your ceramics capacitor catalog for the rms current ratings. frequency (mhz) 30 dbv/m 30 70 128.1 226.2 324.3 10 60 20 0 ?10 50 40 422.4 520.5 618.6 716.7 814.8 912.9 1010 en55022 class b limit 4612 f04 to attenuate the high frequency noise, extra input capacitors should be connected to the v in pads and placed before the high frequency inductor to form the filter. one of these low esr ceramic input capacitors is recommended to be close to the connection into the system board. a large bulk 100f capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. figure 4 shows the radiated emi test results to meet the en55022 class b limit. for different applica - tions, input capacitance may be varied to meet different radiated emi limits.
ltm4612 14 4612fb a pplica t ions i n f or m a t ion output capacitors the ltm4612 is designed for low output voltage ripple. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient requirements. c out can be low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitor. the typical capacitance is 150f if all ceramic output capacitors are used. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 2a/s transient. the table optimizes total equivalent esr and total bulk capacitance to maximize transient performance. multiphase operation with multiple ltm4612 devices in parallel will also lower the effective output ripple current due to the phase interleaving operation. refer to figure 5 for the normalized output ripple current versus the duty cycle. figure 5 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. for example, each phases inductor ripple current dir at zero duty cycle is ~4.3a for a 36v to 12v design. the duty cycle is about 0.33. the 2-phase curve has a ratio of ~0.33 for a duty cycle of 0.33. this 0.33 ratio of output ripple current to the inductor ripple current dir at 4.3a equals 1.4a of the output ripple current (di l ). the output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (esr) of the output bulk capacitance. the equation is: d v out(p-p) d i l 8 ? f ? n ? c out ? ? ? ? ? ? + esr ? d i l where f is the frequency and n is the number of paralleled phases. duty cycle (v o /v in ) 0.1 0.15 0.2 0.25 0.350.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4612 f05 6-phase 4-phase 3-phase 2-phase 1-phase peak-to-peak output ripple current dir ratio = figure 5. normalized output ripple current vs duty cycle, dlr = v o t/l i
ltm4612 15 4612fb figure 6. coincident tracking figure 7. coincident output tracking output voltage time 4612 f07 master output slave output a pplica t ions i n f or m a t ion fault conditions: current limit and overcurrent foldback ltm4612 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady state operation, but also in transient. to further limit current in the event of an overload condi - tion, the ltm4612 provides foldback current limiting. if the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. soft-start and tracking the track/ss pin provides a means to either soft-start the regulator or track it to a different power supply. a capacitor on this pin will program the ramp rate of the output voltage. a 1.5a current source will charge up the external soft-start capacitor to 80% of the 0.6v internal voltage reference plus or minus any margin delta. this will control the ramp of the internal reference and the output voltage. the total soft-start time can be calculated as: t softstart ? 0.8 ? 0.6 0.6 ? v out margin % ( ) ? c ss 1.5a if the run pin falls below 2.5v, then the soft-start pin is reset to allow for the proper soft-start again. current foldback and force continuous mode are disabled during the soft-start process. the soft-start function can also be used to control the output ramp rising time, so that another regulator can be easily tracked. output voltage tracking output voltage tracking can be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure 6 shows an example of coincident tracking where the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider. ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. the master output must be greater than the slave output for the tracking to work. figure 7 shows the coincident output tracking. tracking can be achieved by a few simple calculations and the slew rate value applied to the masters track pin. the track pin has a control range from 0 to 0.6v. the masters track pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: mr sr ? 100k = r2 where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r2 is equal the 100k. r1 is derived from equation: r1 = 0.6v v fb 100k + v fb r fb ? v track r2 pgood run comp intv cc drv cc track/ss f set v out v fb fcb marg0 marg1 mpgm track control pllin ltm4612 r fb 5.23k 100k 10f master output r2 100k c out slave output 4612 f06 c in v in v d pgnd sgnd v in r1 5.23k
ltm4612 16 4612fb where v fb is the feedback voltage reference of the regula- tor, and v track is 0.6v. since r2 is equal to the 100k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r1 is equal to r fb with v fb = v track . therefore r2 = 100k, and r1 = 5.23k in figure 6. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r2 can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example, mr = 1.5v/1ms, and sr = 1.2v/1ms. then r2 = 125k. solve for r1 to equal to 5.18k. each of the track pins will have the 1.5a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 100k is used then a 10k can be used to reduce the track pin offset to a negligible value. run enable the run pin is used to enable the power module. the pin has an internal 5.1v zener to ground. the pin can be driven with 5v logic levels. the run pin can also be used as an undervoltage lockout (uvlo) function by connecting a resistor divider from the input supply to the run pin. the equation for uvlo threshold: v uvlo = r a + r b r b ? 1.5v where r a is the top resistor, and r b is the bottom resistor. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point, and tracks with margining. comp pin the pin is the external compensation pin. the module has already been internally compensated for most output volt- ages. ltpowercad? from linear technology is available for more control loop optimization. fcb pin the fcb pin determines whether the bottom mosfet re - mains on when current reverses in the inductor. tying this pin above its 0.6v threshold enables discontinuous operation where the bottom mosfet turns off when inductor current reverses. fcb pin below the 0.6v threshold forces continu - ous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. pllin pin the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows the internal top mosfet turn-on to be locked to the rising edge of the external clock. the frequency range is 30% around the set operating frequency. a pulse detection circuit is used to detect a clock on the pllin pin to turn on the phase-locked loop. the pulse width of the clock has to be at least 400ns. the clock high level must be greater than 1.7v and clock low level below 0.3v. during the start-up of the regulator, the phase-locked loop function is disabled. intv cc and drv cc connection an internal low dropout regulator produces an internal 5v supply that powers the control circuitry and drv cc for driving the internal power mosfets. therefore, if the system does not have a 5v power rail, the ltm4612 can be directly powered by v in . the gate driver current through the ldo is about 20ma. the internal ldo power dissipation can be calculated as: p ldo_loss = 20ma ? (v in C 5v) the ltm4612 also provides the external gate driver voltage pin drv cc . if there is a 5v rail in the system, it is recom- mended to connect the drv cc pin to the external 5v rail. this is especially true for higher input voltages. do not apply more than 6v to the drv cc pin. a pplica t ions i n f or m a t ion
ltm4612 17 4612fb figure 8. radiated emission scan with 24v in to 5v out at 5a measured in 10 meter chamber frequency (mhz) 30 dbv/m 30 70 128.1 226.2 324.3 10 60 20 0 ?10 50 40 422.4 520.5 618.6 716.7 814.8 912.9 1010 en55022 class b limit 4612 f08 a pplica t ions i n f or m a t ion parallel operation the ltm4612 device is an inherently current mode con - trolled device. this allows the paralleled modules to have very good current sharing and balanced thermal on the design. figure 21 shows a schematic of the parallel design. the voltage feedback equation changes with the variable n as modules are paralleled. the equation: r fb = 100k n v out 0.6v ? 1 n is the number of paralleled modules. radiated emi noise high radiated emi noise is a disadvantage for switching regulators by nature. fast switching turn-on and turn-off make the large di/dt change in the converters, which act as the radiation sources in most systems. ltm4612 inte - grates the feature to minimize the radiated emi noise to meet the most applications with low noise requirements. an optimized gate driver for the mosfet and a noise cancellation network are installed inside the ltm4612 to achieve the low radiated emi noise. figure 8 shows a typical example for the ltm4612 to meet the class b of en55022 radiated emission limit. thermal considerations and output current derating in different applications, ltm4612 operates in a variety of thermal environments. the maximum output current is limited by the environment thermal condition. sufficient cooling should be provided to help ensure reliable opera- tion. when the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. the power loss curves in figures 9 and 10 can be used in coordination with the load current derating curves in figures 11 to 16 for calculating an approximate ja for the module. graph designation delineates between no heat sink, and a bga heat sink. each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 125c maximum. this will maintain the maximum operat- ing temperature below 125c. each of the derating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate ja of the condition. each figure has three curves that are taken at three different air flow conditions. each of the derating curves in figures 11 to 16 can be used with the appropriate power loss curve in either figure 9 or figure 10 to derive an approximate ja . table 3 provides the ap - proximate ja for figures 11 to 16. a complete explanation of the thermal characteristics is provided in the thermal application note, an110.
ltm4612 18 4612fb a pplica t ions i n f or m a t ion figure 9. power loss at 12v out and 15v out figure 10. power loss at 5v out figure 11. no heat sink with 36v in to 5v out figure 12. bga heat sink with 36v in to 5v out figure 13. no heat sink with 24v in to 12v out figure 14. bga heat sink with 24v in to 12v out load current (a) 0 power loss (w) 4 5 3 2 2 4 1 3 5 1 0 6 4612 f09 24v in to 12v out 36v in to 15v out load current (a) 0 power loss (w) 4 5 3 2 2 4 1 3 5 1 0 6 4612 f10 36v in to 5v out ambient temperature (c) 25 0 load current (a) 1.0 2.0 3.0 35 45 55 65 8575 95 4.0 5.0 0.5 1.5 2.5 3.5 4.5 105 4612 f11 0lfm 400lfm 200 lfm ambient temperature (c) 25 0 load current (a) 1.0 2.0 3.0 35 45 55 65 8575 95 4.0 5.0 0.5 1.5 2.5 3.5 4.5 105 4612 f12 0lfm 400lfm 200 lfm ambient temperature (c) 25 0 load current (a) 1.0 2.0 3.0 35 45 55 65 8575 95 4.0 5.0 0.5 1.5 2.5 3.5 4.5 105 4612 f13 0lfm 400lfm 200 lfm ambient temperature (c) 25 0 load current (a) 1.0 2.0 3.0 35 45 55 65 8575 95 4.0 5.0 0.5 1.5 2.5 3.5 4.5 105 4612 f14 0lfm 400lfm 200 lfm figure 15. no heat sink with 36v in to 15v out figure 16. bga heat sink with 36v in to 15v out ambient temperature (c) 25 0 load current (a) 1.0 2.0 3.0 35 45 55 65 8575 95 4.0 5.0 0.5 1.5 2.5 3.5 4.5 4612 f15 0lfm 400lfm 200lfm ambient temperature (c) 25 0 load current (a) 1.0 2.0 3.0 35 45 55 65 8575 95 4.0 5.0 0.5 1.5 2.5 3.5 4.5 4612 f16 0lfm 400lfm 200lfm
ltm4612 19 4612fb a pplica t ions i n f or m a t ion table 3. 12v and 15v outputs derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 11, 13, 15 24, 36 figure 9 0 none 13 figures 11, 13, 15 24, 36 figure 9 200 none 9.3 figures 11, 13, 15 24, 36 figure 9 400 none 8.3 figures 12, 14, 16 24, 36 figure 9 0 bga heat sink 12.2 figures 12, 14, 16 24, 36 figure 9 200 bga heat sink 8.6 figures 12, 14, 16 24, 36 figure 9 400 bga heat sink 7.7 table 4. 5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figure 11 36 figure 10 0 none 14.9 figure 11 36 figure 10 200 none 11.1 figure 11 36 figure 10 400 none 10 figure 12 36 figure 10 0 bga heat sink 14 figure 12 36 figure 10 200 bga heat sink 10.4 figure 12 36 figure 10 400 bga heat sink 9.3 heat sink manufacturer wakefield engineering part no: ltn20069 phone: 603-635-2800
ltm4612 20 4612fb a pplica t ions i n f or m a t ion safety considerations the ltm4612 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. layout checklist/example the high integration of ltm4612 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid - erations are still necessary. ? use large pcb copper areas for high current path, in- cluding v in , pgnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci- tors next to the v d , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? use round corners for the pcb copper layer to minimize the radiated noise. ? t o minimize the emi noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on pads. ? if vias are placed onto the pads, the the vias must be capped. ? interstitial via placement can also be used if necessary . ? use a separated sgnd ground copper area for com- ponents connected to signal pins. connect the sgnd to pgnd underneath the unit. ? place one or more high frequency ceramic capacitors close to the connection into the system board. figure 17 gives a good example of the recommended layout. figure 17. recommended pcb layout signal gnd v out v in gnd c out c in c in c out 4612 f17
ltm4612 21 4612fb a pplica t ions i n f or m a t ion figure 19. typical 5v to 36v in , 3.3v at 5a design with 400khz frequency figure 18. typical 22v to 36v in , 12v at 5a design pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb pull-up supply 5v r3 100k c4 0.01f c3 22pf c out1 22f 6.3v c out2 220f 6.3v c in 10f 50v ceramic v in 5v to 36v clock sync refer to table 2 external 5v supply improves efficiency? especially for high input voltages on/off ltm4612 sgnd pgnd margin control r4 100k r fset 191k 1% r fb 22.1k r1 392k 5% margin + 4612 f19 v d v in pllin c1 10f 50v v out 3.3v 5a pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb pull-up supply 5v r3 100k c4 0.01f c3 22pf c out1 22f 16v c out2 220f 16v c in 10f 50v ceramic v in 22v to 36v clock sync refer to table 2 on/off ltm4612 sgnd pgnd margin control r4 100k r fb 5.23k r1 392k 5% margin + 4612 f18 v d v in pllin c1 10f 50v r5 2m v out 12v 5a
ltm4612 22 4612fb figure 21. 2-phase, parallel 12v at 10a design figure 20. 26v to 36v in , 15v at 4a design with reduced frequency pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb pull-up supply 5v r3 100k c4 0.01f c3 22pf c out1 22f 16v c out2 220f 16v c in 10f 50v ceramic v in 26v to 36v clock sync on/off ltm4612 sgnd pgnd margin control r4 100k r fb 4.12k r fset 806k, 1% r1 392k 5% margin + 4612 f20 v d v in pllin c1 10f 50v v out 15v 4a a pplica t ions i n f or m a t ion pgood run comp intv cc drv cc f set track/ss v out v fb fcb marg0 marg1 mpgm pull-up supply 5v r2 100k c7 0.33f c6 47pf c3 22f 16v 4612 f21 c4 220f 16v c11 0.1f c5 100f 50v c2 10f 50v c8 10f 50v v in 20v to 36v ltc6908-1 2-phase oscillator clock sync 0 phase clock sync 180 phase ltm4612 sgnd pgnd pgood run comp intv cc drv cc f set track/ss ltm4612 sgnd pgnd margin control 5% margin r4 100k r fb 2.61k r1 392k r5 124k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c9 22f 16v c10 220f 16v r6 392k + + r fb = 100k/n v out 0.6v ? 1 v d v in pllin c1 10f 50v v d v in pllin c11 10f 50v v out 12v, 10a
ltm4612 23 4612fb figure 22. 2-phase, 12v and 10v at 5a design a pplica t ions i n f or m a t ion pgood run comp intv cc drv cc f set track/ss v out v fb fcb marg0 marg1 mpgm pull-up supply 5v r2 100k c7 0.15f c6 22pf c3 22f 16v 4612 f22 c4 220f 16v 12v at 5a c11 0.1f c5 100f 50v c2 10f 50v c8 10f 50v v in 22v to 36v ltc6908-1 2-phase oscillator clock sync 0 phase clock sync 180 phase ltm4612 sgnd pgnd pgood run comp intv cc drv cc f set track/ss ltm4612 sgnd 12v track pgnd margin control 5% margin r4 100k r fb1 5.23k r fb2 6.34k r1 392k r8 100k r9 6.34k r3 100k r7 100k pull-up supply 5v r5 118k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c1 22pf c9 22f 16v c10 220f 16v 10v at 5a margin control r6 392k + + v d v in pllin c1 10f 50v v d v in pllin c11 10f 50v
ltm4612 24 4612fb drv cc f set track/ss pgood run comp intv cc fcb marg0 marg1 mpgm v out v fb v d v in 5v r2 100k c7 0.15f c6 22pf c3 22f 6.3v 4612 f23 c4 220f 6.3v 5v at 5a c11 0.1f c5 100f 50v c2 10f 50v c8 10f 50v v in 7v to 36v ltc6908-1 2-phase oscillator pllin clock sync 0 phase clock sync 180 phase sgnd pgnd pgood run comp intv cc drv cc f set track/ss v in v d pllin sgnd 5v track pgnd margin control r4 100k r fset1 150k r fb1 13.7k r1 392k r8 100k r9 22.1k r fset2 100k r3 100k r7 100k 3.3v r5 200k v + gnd set out1 out2 mod + v out v fb fcb marg0 marg1 mpgm c1 22pf c9 22f 6.3v c10 220f 6.3v 3.3v at 5a margin control r fb2 22.1k r6 392k + + ltm4612 ltm4612 5% margin c1 10f 50v c11 10f 50v figure 23. 2-phase, 5v and 3.3v at 5a design with 500khz frequency a pplica t ions i n f or m a t ion
ltm4612 25 4612fb pin name a1 a2 a3 a4 a5 a6 v in v in v in v in v in v in b1 b2 b3 b4 b5 b6 v in v in v in v in v in v in c1 c2 c3 c4 c5 c6 v in v in v in v in v in v in pin assignment tables (arranged by pin function) pin name d1 d2 d3 d4 d5 d6 pgnd pgnd pgnd pgnd pgnd pgnd e1 e2 e3 e4 e5 e6 e7 e8 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd f1 f2 f3 f4 f5 f6 f7 f8 f9 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pin name j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 v out v out v out v out v out v out v out v out v out v out v out k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 v out v out v out v out v out v out v out v out v out v out v out l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 v out v out v out v out v out v out v out v out v out v out v out m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 v out v out v out v out v out v out v out v out v out v out v out pin name a7 a8 a9 a10 a11 a12 intv cc pllin track/ss run comp mpgm b7 b8 b9 b10 b11 b12 v d - run - mpgm f set c7 c8 c9 c10 c11 c12 v d - - drv cc marg1 marg0 d7 d8 d9 d10 d11 d12 - - sgnd - comp marg1 e9 e10 e11 e12 - - drv cc drv cc f10 f11 f12 - - v fb g12 pgood h12 sgnd j12 nc k12 nc l12 nc m12 fcb p ackage descrip t ion
ltm4612 26 4612fb p ackage descrip t ion lga package 133-lead (15mm 15mm 2.82mm) (reference ltm dwg # 05-08-1766 rev ?) l k j h g f e d c b m a notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 133 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.10 0.10 0.05 2.72 ? 2.92 detail b detail b substrate mold cap 0.27 ? 0.37 2.45 ? 2.55 bbb z z 15 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 13.97 bsc 1.27 bsc 13.97 bsc 0.12 ? 0.28 package bottom view c(0.30) pad 1 3 pads see notes 1 2 3 4 5 6 7 8 10 9 11 12 detail a 0.630 0.025 sq. 133x s yxeee suggested pcb layout top view 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 lga 133 1107 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1?
ltm4612 27 4612fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 03/10 changes to title and description changes to absolute maximum ratings changes to electrical characteristics text changes to operation section text changes to applications information section changes to figures 18, 19, 20, 21, 22 changes to related parts 1 1 2, 3 10 12, 14 19, 20, 21, 22 26 b 05/11 changes to the title, description, features and typical application sections. changes to the l denotes... statement and note 2. changes to the pin functions. changes to the block diagram. text changes to the operation section. text changes to the applications information section. changes to figures 17, 19, 21, 22. changes to the related parts. 1 2, 3, 4 7, 8 9 10 10C20 20, 21, 22, 23 28
ltm4612 28 4612fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2008 lt 0511 rev b ? printed in usa r ela t e d p ar t s p ackage p ho t ograph 4612 f24 15mm 15mm 2.8mm part number description comments ltm4606 en55022b compliant 6a, dc/dc module regulator en55022b compliant with pll, output tracking and margining, ltm4612 pin compatible ltm4613 en55022b compliant 36v, 8a, step-down module regulator with pll, output tracking 5v v in 36v, 3.3v v out 15v, 15mm 15mm 4.3mm lga package ltm4601/ltm4601a 12a dc/dc module regulator with pll, output tracking/margining and remote sensing synchronizable, polyphase operation, ltm4601-1/ltm4601a-1 version has no remote sensing, lga package ltm4604a low v in 4a dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 9mm = 15mm = 2.3mm lga package ltm4608a low v in 8a dc/dc module regulator 2.7v v in 5.5v, 0.6v v out 5v, 9mm = 15mm = 2.8mm lga package ltm8022/ltm8023 36v in , 1a and 2a dc/dc module regulator pin compatible, 4.5v v in 36v; 9mm = 11.25mm = 2.8mm lga package LTM4627 20v in , 15a dc/dc step-down module regulator 4.5v v in 20v, 0.6v v out 5v, 15mm 15mm 4.3mm lga package ltm4618 26v in , 6a dc/dc step-down module regulator with pll, output tracking 4.5v v in 26.5v, 0.8v v out 5v, synchronizable, 9mm 15mm 4.3mm lga package ltm8033 en55022b compliant 36v in , 3a dc/dc step-down module regulator 3.6v v in 36v, 0.8v v out 24v, synchronizable, 11.25mm 15mm 4.3mm lga package

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